What's New

NOTE: The Jupyter Notebook below is included in the Chimera SDK and can be run interactively by running the following CLI command:

$ quadric sdk notebook

From the Jupyter Notebook window in your browser, select the notebook named /quadric/sdk-cli/examples/doc_template/whats_new.ipynb.

Quadric Chimera SDK 26.08 – What's New

A Chimera assembling from its parts — the building blocks become whole models.

26.08 is a monthly MINOR release, rolling up 26.07 → 26.08. 26.07 landed MoE routing and Gated DeltaNet as sweep-tested kernels; 26.08 assembles them into Qwen3.6's hybrid decoder block. WaveFormer arrives as a new workload family, DETR-R101 sheds its last custom op, and the quantization library ships with the SDK.

Summary

• The Simulator Is Faster: ISS ~1.3–1.5× on ResNet-18 and Qwen, no change to numeric output. Learn More
• DETR-R101 Runs Fully Native: Decoder custom op gone, all 17 attention cores lower natively. 25.9M → 18.5M cycles (−28%), ≥80% box-agreement gate still clearing. Learn More
• WaveFormer, a New Workload Family on QC-N: INT8 sEMG gesture classifier, one custom op, argmax matching ONNX Runtime within 5 quantization steps. Learn More
• Qwen3.6's Hybrid Decoder Block: Three Gated DeltaNet layers + one gated-attention layer — one A-A-A-B instance — assembled and ISS-validated, plus a whole-sequence DeltaNet prefill. Learn More
• pi0.5 VLA −14% End to End: Fused gate+up MLP, 14.17M → 12.16M cycles at seq=968 on 8 cores. Learn More
• INT4 Weights Get a Fast Path: DoubleINT8 W4A16 matmul — INT4 weights on INT8 MACs, INT32 accumulation, ~1.7× the FP16 dequant path with lower error. Learn More
• Vision Pipelines Speed Up: SegFormer ~1.6× at 512×512; HRNet-family resize −36.9%. Learn More
• Quantization Library Ships With the SDK: quadric_pyquant, on PyTorch 2.13 + transformers v5. Models quantized with a stale copy must be re-quantized. Learn More

Detailed Changes

Detailed Changes

Dev Studio

New Notebooks!

• WaveFormer INT8 → QC-N: INT8 sEMG gesture classifier, 6 encoder blocks, 8 heads, seq 161. One custom op per block (nn::waveAttentionOp); patch convolution, all 15 LayerNorms, both residual QLinearAdds, the FFN and projection QGemms, and the CLS head all native. Argmax matches ONNX Runtime; max per-logit error 5 output-quantization steps (0.423) against a ~19-step argmax margin, threshold 6. QC-N: 8×8 PE array, 4 MB L2, 8 MACs/PE, 0.5 GHz.
• VGG-16 A8W4: INT4 weights on the three classifier Gemm layers. One call builds the A8W8 baseline, the A8W4 QDQ model for ONNX Runtime comparison, and the A8W4 custom-op model for CGC. 1000 images, QC-U at 1.5 GHz / 16 MACs/PE / 32 GBps: Top-1 76.20% FP32, 75.60% A8W8, 75.50% A8W4, −36.6% cycles.

Notebook Updates

• DETR-R101 decoder attention lowers natively. Flow drops from quantize → custom-op → compile to quantize → compile: 25.9M → 18.5M cycles (−28%), QC-U 8 MB L2 / 4 kB LRM / 16 MACs/PE / 1.56 GHz, single core. All 17 attention cores detected: 6 encoder self (seq 360→360), 5 decoder self (100→100), 6 decoder cross (100→360), including the constant-Q layer-0 cross-attention. ≥80% box-agreement gate unchanged and clearing; validation now like-for-like, both sides running the same quantized graph. Requires patch-mesh pause (CGC).
• pi0.5 fused gate+up MLP: fused gate_proj + GELU + up_proj + mul_quantize in prefill and action-expert stages. K=2048 accumulates in two passes, not three. ISS, 8 cores, seq=968: 14,172,064 → 12,155,644 (−14.2%); 33.65M → 29.54M (−12.2%) at 2 prefills + 10 expert steps. Staged path retained byte-identical as fallback.
• Whisper: decoder validation gate requires a top-3 ordered match.
• Docs: SegFormer and DETR end-to-end pages added; obsolete standalone DETR encoder notebook removed, demo index repointed. sdk source --stack-overflow-error promotes stack-overflow detection to an error (opt-in).

Core

CGC

• Patch-mesh pause — native attention on QC-U. The mesh suspends mid-computation so its consumer drains the INT32 QK score tile in place, instead of the tile having to fit 4 kB LRM. Where the mesh output fits the scratch ring the plan yields one non-pausing iteration, so smaller configurations are unchanged. Unlocks DETR-R101's 17 native attention cores.
• SegFormer, tile-block layout throughout — ~1.6× at 512×512. Multi-MROI attention takes 4-D NCHW directly (byte-identical to flat when the innermost dimension is aligned); the optimizer absorbs the spatial flatten and re-emits it below the op, cancelling the reshapes that bracketed every attention block. At 256×512: 11.98M → 8.96M cycles (~1.34×) — the gain scales with how much of the network the flatten crosses.
• Resize — HRNet-family −36.9%. Native on-array bilinear extends from 2×-only to exact-4× INT8 half_pixel; redundant N×↑ → 0.5×↓ chains collapse to one (N/2)× resize (exact when N % 4 == 0). 34.15M → 21.55M cycles, MAC utilization 4.7% → 7.5%, on a network where 47 of 50 resizes previously took the opaque L2-to-L2 path. Synthetic calibration.
• ViT-B/16 compiles at 1024×1024. Activations exceeding the 8 MB L2 split through external memory, LayerNorm streamed from DDR. DDR-resident custom-op outputs excluded from L2 liveness.
• Native PyTorch ops in torch.export. Plain ATen glue between opaque modules no longer fails compilation: shape ops (reshape, view, permute, transpose, unsqueeze, squeeze), arithmetic (add, sub, mul, div, neg), no-ops (clone, contiguous) — each shape-checked against torch.
• New operators: ONNX ScatterND end to end, GatherElements, 2-D LayerNorm, quantized patch merge (QuantizeLinear + QLinearConcat), constant-prepend to a computed tensor, general global average pool.
• Gathers hoist through single-axis norms. A norm reducing over one axis is separable along the others, so a take on its output moves above it and the norm runs on gathered rows only. WaveFormer normalizes 161 tokens then gathers the CLS row — 160 of 161 rows were dead. Same shape as any ViT/BERT CLS head.
• External buffering flags: enable_input_ext_buffering, enable_output_ext_buffering on ChimeraJob, default False. 0.5–1% on mobilenetv2-, centernet- and hrnet-class networks.
• Clock floor 0.9 → 0.5 GHz, so the ISS models 500 MHz targets. Activation-LUT init hoisting opt-in via enable_lut_hoist. RMS and group/layer-norm standard deviation route through full-precision INT64 accumulators.

CCL

• Qwen3.6 gated attention, FP16 decode. GQA core plus QK-norm, RoPE, KV-cache reuse, sigmoid output gate, output projection; validated against the pinned Hugging Face reference. Fixed-point→FP16 conversions fold into producer egress, the sigmoid gate fuses into the attention core as a per-core post-process, Q RoPE distributes per core, decode matmuls take the full on-chip weight budget. The rectangular 4096 → 2048 output projection is now expressible — bit-identical wherever attention and residual widths are equal, which is every prior configuration.
• Gated DeltaNet prefill. A whole-sequence layer replaces the per-token recurrence with one chunked call over all tokens; correlation 1.0, relative error ~1.3e-3 vs the decode path's float64 reference. A blocked triangular solve replaces whole-chunk Neumann doubling, whose intermediates grow binomially: near-duplicate keys with weak decay overflowed the fixed-point scratch and returned a finite, saturated, wrong answer — no NaN, no crash, and missed by a sweep drawing only decorrelated keys.
• MoE decode block. Full Qwen3.5-MoE block as routed + sigmoid(x·Wsg)·shared. One fused first-layer matmul produces the shared gate/up projections, the output-gate logit and all 256 router logits; then softmax → top-k → renormalization into a single L2 accumulator. Standalone router gains an optional quantized weight.
• WaveFormer kernels (q8/m8 — q/m is PE-array dimension over MACs per PE — 8 heads, head_dim 32, seq 161). Hybrid flash attention: INT8 Q·Kᵀ, FP16 A·V, the precision the exported model uses. Interleaved (GPT-J) RoPE reduces to the existing split-half kernel bit-exactly, Q·Kᵀ being a per-head dot product and invariant to a shared permutation of the head dimension. That de-interleave is a static column permutation of the qkv output, so it is baked into the weight order offline and deleted: 1,179,985 → 916,030 cycles (−22.3%) single-core, block-0 fixture. erf-GELU folds into the first matmul's epilogue via a LUT: 294,687 → 111,147 (−62%). Reduced-query mode computes the final block's attention for the CLS read-out rows only: 915,226 → 439,684 (−52.0%), computed rows bit-identical.
• DeepSeek-V4 compressed attention, building blocks. Persistent compressor cache for the compressed-sparse and heavily-compressed memory branches with DDR-to-L2 primitives; FP16 low-rank projection + RMS-norm producing pre-RoPE queries and key/values; decoupled interleaved RoPE, adjacent pairs against half-sized tables, trailing columns only.
• Runtime-shaped matmuls. An INT8 matmul compiled for a maximum shape MACs and broadcasts only the real K, not the padded tile width. FP16 gains the same, so an attention matmul compiled for a maximum sequence length runs efficiently at a shorter one.
• W4A16 DoubleINT8 — ~1.7× the FP16 path at prefill M=64, q16/m16, 4 cores. Activations dynamically quantize to INT16 on a per-invocation abs-max scale, split into two INT8 byte planes, MAC in INT8, recombine with INT32 accumulation. Covers asymmetric AWQ and symmetric weights. Faster and more accurate than dequantizing INT4 to FP16: INT8 MACs run at twice FP16 throughput, and INT32 accumulation avoids FP16 partial-sum collapse. Non-block-aligned shapes fall back to FP16.
• Gate+up FFN three-path dispatch. Compile-time choice: pin the per-PE weight column and stream activations (small K); pin whole-M output accumulators and stream double-buffered weights (small M, decode); or a general fallback holding partials in L2 — each gated on exact L2 accounting, not a fixed margin. At q32/m16: qwen3-8B prefill −14.6% (decode neutral), two small-K shapes −13.4% and −12.3%, pi0.5 MLP −54.8% at 1 core / −56.9% at 8.
• LiDAR voxelization. Hard-voxelization kernel for BEVFusion-style branches: assigns points to voxels, deduplicates, computes per-voxel counts and coordinate means via a stable radix sort plus segmented reduce, output positions from a cross-PE prefix sum. Average voxel pooling ~1.94× on QC-U (1.22M → 631K cycles, BEVFormer case).
• Patch-mesh pause gains a public API, general-multihead-attention-head support, and a caller-supplied LRM budget. Quantization tails round ties toward positive infinity, matching the direction of the pre-round shift's floor error.

LLVM

• MEU-shadow scheduling — 1.042× on YOLOX-tiny (12.69M → 12.18M cycles; QC-N, 8 MACs/PE, 1 core, 1.7 GHz), ISS outputs unchanged. Accumulator-sum reads sink into the MEU shadow, placed before first use rather than immediately after the accumulator instruction, so they stop delaying the next launch in a software-pipelined convolution loop; register-sourced fixed-register writes hoist above it.
• New diagnostic at compile time when a parameter is a pointer or reference to a heterogeneous struct, which cannot be passed as a function argument in GPNPU programs.
• User compiler flags pass as distinct arguments rather than appended onto the feature string, where the backend rejected them as an unknown feature and silently ignored them — leaving the dispatcher stack limit at its 4 KiB default and failing any model needing more. ViT-B/16 at 1024×1024 needs 4608 B.

ISS / Archsim Performance

• The simulator is faster: ~1.3–1.5× on ResNet-18 and Qwen, no regressions across the suite, no change to numeric output. Five hot-path optimization efforts land as one benchmarked stack of equivalence transforms removing redundant per-core and per-cycle work.
• Consolidation: three ISS variants collapse into one owning a vector of clusters. One intentional behavior change — a single-core cluster no longer registers a coalescer channel, coalescing being intra-cluster.
• Power profiling no longer segfaults in the ISS host harness. The harness and the simulator library each vendored a different version of the same JSON library, exporting identically-named weak symbols across a changed struct layout; the dynamic linker merged them.

Bug Fixes

• 3×3 stride-2 convolution corrupted at VAP partition edges. The data-aggregation path moves data across physical neighbor ports to build the receptive field, but that movement coincides with the logical tensor edge only for the first VAP partition — every other partition read the adjacent partition's data instead of its own edge padding. Fixed for 3×3; larger kernels tracked.
• nmsIou API compatibility restored — explicitly typed array overload across all three quantized-variable arrays, plain-array signature retained as deprecated. No numerical change.
• ONNX Clip with a single bound was silently converted to a passthrough, dropping the clamp and crashing shape canonicalization downstream.
• Compilation and lowering: channel-split max-pool output-buffer overrun; corrupt 2× bilinear resize when the external split lands on the resize's inputs; a custom op fed by a global average pool; binary-op broadcast for axis-0 and scalar operands; matmul bias handling on the native kernel path; a ViT layout-adaptation failure for multi-argument ops with scalar arguments; a broadcast constant sinking past an affine-mapped axis.

Breaking Changes & Migration Notes

Two actions for quantization users: repoint and re-quantize against the packaged quadric_pyquant, and rebuild the environment on the new pins. Direct callers of removed kernel entry points have compile-time work; the rest are re-baselines. Detail in the Migration Guide.

• Quantization library ships as quadric_pyquant with the SDK. Repoint imports and re-quantize any model calibrated with an older in-tree copy: converters are keyed by class object, so classes from a stale copy match nothing, export traces into every quantized layer, and the graph is unconvertible. Nothing fails at import.
• Requires PyTorch 2.13 + transformers v5 — torch 2.13.0+cu129, torchvision 0.28.0, torchcodec 0.13.x, transformers 5.14.1, Python 3.10.
• Fourteen kernel-library functions removed: memcpy, trunc, vectorMag, loadTensors, argmaxImpl, argmax, vectorAngle, writeTensor, asCast, stdRound, blockUntilPaused, invokeTilewiseArray, transpose, invokeTilewise — all chimera:: entry points, each removal CI-verified. memcpy is the removed spelling; memCpy is the supported kernel.
• nn::qwen3PrefillGateUpProjection deprecated, removal in 26.09 — still compiles, emits a diagnostic naming nn::gateUpProjection. unloadAndCompareTensors() also deprecated; nmsIou's plain-array signature becomes a deprecated overload.
• Quantization tails round ties toward positive infinity — INT8 output on affected paths can differ by one LSB from 26.07.
• ISS cycle counts can shift on single-core-per-cluster devices, which no longer register a coalescer channel. Multi-core clusters unaffected.

What's next: Qwen3.6 decode is assembled and validated but not quantized; that and the end-to-end Qwen3.5-MoE pipeline are tracked separately. The DeepSeek-V4 building blocks await their attention math and end-to-end assembly.

Performance Summary

No regressions. All 25 top movers vs 26.07 are positive, +7.8% to +16.3%. YOLOX leads — yolox-tiny +16.3% (QC-U-16MB, QC-P-8MB), +15.0% (QC-N-8MB); yolox-s +13.5–13.8% on the same three. Then the YOLOP backbone across QC-N/P/U at 1–8 cores (+7.8–9.3%), DDRNet23-slim +9.8%, EfficientNet-EM/EL +8.6%. The MEU-shadow scheduling fixes lift the convolutional fleet broadly — EfficientNet, DDRNet, ResNet, U-Net and CSPDarknet as much as or more than the YOLO family that motivated the work.

From release PR benchmarks:

• Simulator: ISS ~1.3–1.5× on ResNet-18 and Qwen, no change to numeric output.
• DETR-R101 end to end: 25.9M → 18.5M cycles (−28%), QC-U 8 MB L2 / 4 kB LRM / 16 MACs/PE / 1.56 GHz, single core. ≥80% box-agreement gate unchanged and clearing.
• pi0.5 fused VLA: 14.17M → 12.16M cycles (−14.2%) at seq=968 on 8 cores. MLP kernel alone −54.8% at 1 core, −56.9% at 8 (q32/m16).
• HRNet-family resize: 34.15M → 21.55M cycles (−36.9%), MAC utilization 4.7% → 7.5%. Synthetic calibration.
• WaveFormer attention: 1,179,985 → 916,030 cycles (−22.3%) single-core, q8/m8, seq 161, block-0 fixture.

Two changes move baselines rather than deliver speedups: quantization tails now round ties toward positive infinity (one LSB on affected INT8 paths), and reported ISS cycle counts can shift on single-core-per-cluster devices. Both are in the Migration Guide.

from IPython.display import Image, display
from whats_new_utils import compare_current_release_vs_last_release

release_images = compare_current_release_vs_last_release("26.08", "26.07")
display(Image(release_images[0]))

Migration Guide

Ordered by blast radius.

Quantization Library Ships as quadric_pyquant

What changed: the library is packaged with the SDK rather than living in the compiler tree, with its workload configs, READMEs and scripts in the wheel.

Before (≤26.07):

from tvm.contrib.epu.quadric_quant.layers import QConv2d, QMatMul

After (26.08):

from quadric_pyquant.layers import QConv2d, QMatMul

Action required: repoint imports, and re-quantize any checkpoint calibrated with an older in-tree copy. ChiPy's converters are keyed by class object, so classes from a stale copy match nothing: no submodule is opaque, torch.export traces into every quantized layer, and the graph arrives as raw quantization arithmetic. Nothing fails at import — the symptom is an unconvertible graph. To check first, confirm your model's layer classes import from quadric_pyquant.layers.

Why: two copies meant the converter registry was built from one of them, so a model quantized with the other could not be consumed.

PyTorch 2.13 + transformers v5 Required

What changed: torch 2.13.0+cu129, torchvision 0.28.0, torchcodec 0.13.x, transformers pinned 5.14.1, Python 3.10. Extras restructured into qq-core, qq and per-workload groups; openpi-client is now the published PyPI package.

Action required: recreate the quantization environment on the new pins and install the per-workload extra. If you patched Hugging Face attention yourself, move to the v5 unified attention interface — per-family re-vendored attention is gone.

Why: transformers v5 is required for the newer model families the library supports.

Fourteen Kernel Functions Removed

What changed: thirteen previously deprecated functions — memcpy, trunc, vectorMag, loadTensors, argmaxImpl, argmax, vectorAngle, writeTensor, asCast, stdRound, blockUntilPaused, invokeTilewiseArray, transpose — plus the verified-unused invokeTilewise. All chimera:: entry points. The non-pitched tensor-serialization path is also removed.

Action required: none on the supported API; each removal was CI-verified against sdk-cli and the compiler. Direct callers move to the current equivalents. Note memcpy is the removed spelling and memCpy the supported kernel, so a call site that still compiles may be resolving to the wrong symbol family.

Why: deprecated symbols left indefinitely keep the maintenance and safety-audit surface larger than the shipped API.

nn::qwen3PrefillGateUpProjection Deprecated, Removal in 26.09

What changed: the forwarding wrapper now carries a deprecation attribute with a named removal release.

Before (≤26.07): compiled silently. After (26.08): compiles with a diagnostic naming nn::gateUpProjection.

Action required: migrate to nn::gateUpProjection — same arguments, no behavior change — before 26.09. unloadAndCompareTensors() is also deprecated, and nmsIou's plain-array signature becomes a deprecated overload alongside a typed container::NDArray one.

Why: the SDK's own callers have migrated; the alias now exists only for out-of-tree code.

Quantization Tails Round Ties Toward +inf

What changed: tails that rounded ties away from zero now round toward positive infinity, including the transposed-convolution INT8 tails.

Action required: expect one-LSB differences in INT8 output on affected paths. Re-baseline bit-exact golden vectors against 26.08.

Why: the pre-round shift floors — a sign-independent downward error — while rounding away from zero applied a sign-dependent tie-break on top, so the two compounded on negatives and the error distribution never averaged out. Rounding toward +inf makes it symmetric and matches the convention CGC already states.

ISS Cycle Counts Shift on Single-Core-Per-Cluster Devices

What changed: the three simulator variants collapse into one, and a single-core cluster no longer registers a coalescer channel on the data memory.

Action required: re-baseline ISS cycle counts on single-core-per-cluster configurations. Multi-core clusters are unaffected; otherwise the consolidation is bit-identical with no FPS delta.

Why: coalescing is intra-cluster. A single-core-per-cluster device previously registered a channel that carried no traffic but still arbitrated for bandwidth.