Glossary

APB

Arm AMBA® Advanced Peripheral Bus. APB is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family.

AXI

Arm AMBA® AXI™: Advanced eXtensible Interface. AXI is an on-chip communication bus protocol and is part of the Advanced Microcontroller Bus Architecture (AMBA) specification.

CCL

Chimera Compute Library. The Chimera Compute Library is an application programming interface (API) that makes it possible to write high-performance, data-parallel algorithms targeting Quadric's Chimera GPNPUs. To learn more, refer to Chimera Compute Library (CCL) API.

CGC

Chimera Graph Compiler. The Quadric Chimera Graph Compiler is a powerful conversion and code optimization tool that accepts a quantized Deep Neural Network (DNN) model as input, performs optimizations, and outputs an optimized C++ code representation of the graph utilizing the Chimera Compute Library (CCL) APIs. This C++ representation can then be compiled, alongside more traditional C++ algorithms, by the Chimera LLVM C++ Compiler. CGC is an extension of the popular Apache TVM compiler framework. To learn more, refer to Overview of the CGC.

COCO

COCO is a large-scale object detection, segmentation, and captioning dataset. To learn more, refer to the COCO website.

CUDA®

CUDA® is a NVIDIA® solution for General Purpose Programming on GPUs (Graphics Processing Units).

CV

Computer Vision. A field of artificial intelligence (AI) that teaches computers and systems to derive meaningful information from digital images, videos and other visual inputs.

Chimera

Chimera™ is the brand name for Quadric's GPNPU.

Chimera SDK

The Software Development Kit for Quadric's Chimera™ GPNPU.

DL

Deep Learning. Deep learning is a sub-field of Machine Learning (ML) in which multi-layered neural networks learn from vast amounts of data.

DMA

Direct Memory Access. DMA is a feature of computer systems that allows certain hardware subsystems to access main system memory independently of the CPU.

DNN

Deep Neural Network. An artificial neural network composed of three or more layers, including an input, output, and at least one hidden layer in between.

Dispatcher

The unit that dispatches instructions to the Scalar Element (SE) and Processing Element (PE) of Quadric's Chimera GPNPU architecture.

ELS

External Load/Store. ELS is the external DMA engine that manages data flows between the L2 memory and external memory (often DDR via AXI interface).

FILM

Fusion in Local Memory. A more restrictive definition of operator fusion adopted by Quadric's Chimera Graph Compiler (CGC). In CGC, two successive operations are considered to be fused only if the intermediate tensor between those two operations does not get stored to or loaded from L2 memory; in other words, intermediate tensors must remain in LRM, the lowest level of memory on the Chimera platforms. To learn more, refer to the document on Graph Optimizations Performed by CGC.

GEMM

General matrix multiply, one of the basic Linear Algebra subprograms.

GOPS

Giga [billion] Operations Per Second. A common unit of measurement for instruction-level performance of a processor or system.

GPNPU

General-Purpose Neural Processing Unit. A general-purpose NPU uses a unified processor architecture that can handle matrix and vector operations and scalar (control) code in one execution pipeline. These workloads are traditionally handled separately by some combination of a NPU, DSP, and realtime CPU. The entire architecture is a single software-controlled core, allowing for the simple expression of complex parallel workloads.

ISA

Instruction Set Architecture. An ISA is an abstract model of a processor. In general, an ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA.

ISS

Instruction Set Simulator. An ISS is a simulation model which mimics the behavior of a microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers. An ISS for the Chimera architecture is included in the Chimera SDK to benchmark algorithm performance on hardware.

Note: The Chimera ISS runs significantly slower than any actual hardware instance.

ImageNet

A large visual database curated by the Stanford Vision Lab that has been instrumental in advancing computer vision (CV) and deep learning (DL) research. To learn more, refer to the ImageNet website.

Jupyter Notebook

A Jupyter Notebook, formerly an interactive Python or IPython Notebook, is a JSON file usually ending with the ".ipynb" extension that contains a list of different types of cells: Markdown for text display, Code for executable Python code, and Output for the terminal output of the executable Python code. These notebook files can be executed by Jupyter, a web-based interactive computational environment that is popular among the AI and Data Science communities. Many of Quadric's reference examples are written as Jupyter Notebooks and are included in the Quadric SDK so that users may reproduce the results from the notebooks in their local environment.

L2 Memory

Level 2 Memory. The second closest level of memory from the processing elements of the Chimera GPNPU. To learn more about the Chimera GPNPU's memory hierarchy, refer to Overview of GPNPU Architecture.

Note: In previous versions, this was referred to as OCM. In the current version, you may see ocm in code examples. These examples will be updated in future versions to reflect the new naming convention.

LLVM

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Quadric's C++ compiler builds upon the LLVM compiler infrastructure. To learn more about LLVM, refer to https://llvm.org/. To learn more about Quadric's LLVM C++ compiler, refer to Chimera LLVM C++ Compiler.

LRM

Local Register Memory. A local storage with accesses through the register file pointer registers. Typically holds tensor values.

Lower

Lowering is the transformation of higher level representations to lower level representations. A compiler traditionally lowers a high level language to machine code in one or more steps.

MAC

Multiply–Accumulate Operation. MAC operations are fundamental to many linear algebra operations, such as matrix multiplications, convolutions, and dot products. MACs are often used as a more specific measure of computational complexity in deep learning models that heavily rely on linear algebra operations, such as convolutional neural networks (CNNs).

MEU

MAC Execution Unit. MAC units are fundamental blocks in computing devices, such as digital signal processors (DSP) and neural processing units (NPU), that need to optimize performance of MAC operations.

ML

Machine Learning: A sub-field of Artificial Intelligence (AI) encompassing algorithms whose performance improve as they are exposed to more data over time.

Mapping

In the context of Chimera architecture, mapping means to assign locations to data and code, and design the flow of data in and out of the SIMD core array.

NCHW

N: Number of data samples, C: Image channels, e.g. a red-green-blue (RGB) image will have 3 channels, H: Image height, W: Image width. An acronym describing the order of the dimensions in a tensor containing image data samples. Also, referred to as "channels-first" format.

NHWC

N: Number of data samples, H: Image height, W: Image width, C: Image channels, e.g. a red-green-blue (RGB) image will have 3 channels. An acronym describing the order of the dimensions in a tensor containing image data samples. Also, referred to as "channels-last" format.

NLP

Natural Language Processing. A field of artificial intelligence (AI) that gives computers the ability to interpret, manipulate, and comprehend human language.

ONNX

Open Neural Network Exchange. ONNX is an open-source format for representing DNN models and is designed to enable AI developers to more easily use, compile, and deploy models trained with different Deep Learning (DL) frameworks, e.g. PyTorch, TensorFlow, TensorFlow Lite, Caffe, etc. ONNX accomplishes this by defining a common set of operators - the building blocks of deep learning models - and a conversion paradigm for representing these operators in each of the aforementioned DL frameworks. To learn more about how ONNX is used at Quadric, refer to Accepted Model Formats - Quantized ONNX.

PE

Processing Element(s). PEs are the compute elements of a Chimera GPNPU. PEs are optimized for 8-bit integer (INT8) graph operations with a configurable hardware option to also include 16-bit MAC hardware. In addition to the NN-focused hardware, a full set of math functions is available in each ALU – both in the Scalar Element and the Processing Element (PE) units – to support all forms of complex DSP operations. Refer to Overview of GPNPU Architecture for more info.

PE Array

Processing Element Array. An array of PEs that make up the primary compute elements of a Chimera GPNPU. Refer to Overview of GPNPU Architecture for more info.

PLS

Peripheral Load/Store. PLS is the internal DMA engine of a Chimera core that moves data between L2 memory and LRM.

QB

Refers to the second-generation of Quadric GPNPU processors. Available configurations are QB1, QB4, and QB16. To learn more, refer to Overview of GPNPU Architecture.

RISC

Reduced Instruction Set Computer. RISC is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions rather than the highly-specialized set of instructions typically found in other architectures. RISC is often considered the most efficient CPU architecture technology available today.

SIMD

Single Instruction, Multiple Data. SIMD units refer to hardware components that perform the same operation on multiple data operands concurrently, i.e. in parallel.

Scheduler

Software that takes a frozen graph representation of an algorithm (usually a neural network backbone) and converts it to C++ code.

SoC

System-on-Chip. SoCs are a single microchip that integrates most or all components of a computer or other electronic system. These components almost always include on-chip CPU, memory interfaces, input/output (I/O) devices and interfaces, and secondary storage interfaces. For SoCs designed for AI applications, some combination of graphical processing units (GPU), digital signal processors (DSP), neural processing units (NPU), or general-purpose neural processing units (GPNPU) are often also included.

TOPS

Tera [trillion] Operations Per Second. A common unit of measurement for instruction-level performance of a processor or system.

TVM

An open-source, deep learning compiler stack for CPUs, GPUs, and specialized accelerators. It aims to enable machine learning engineers to optimize and run computations efficiently on any hardware backend. Quadric's Chimera Graph Compiler (CGC) is built on top of the Apache TVM framework. To learn more, refer to https://tvm.apache.org/.

YOLO

You Only Look Once. A family of deep neural network (DNN) architectures for object detection that predict bounding boxes and class probabilities directly from full images in one inference pass.