The Chimera Instruction Set Simulator (ISS) is an executable model of the Chimera GPNPU core that is bundled with the Chimera SDK.
The ISS can be utilized both in a standalone mode to profile and tune application code in isolation, or as a callable SystemC transaction level model, bundled into a more comprehensive virtual prototype of an SoC where more accurate memory model behavior can be used to fine-tune your Chimera code more precisely.
Standalone mode
- Approximately timed model (performance accurate to +/- 5%).
- Models all architectural states to provide debug visibility.
- Models all core-internal LRM RAMs and the L2 RAM.
- Includes a simplistic model of all other memory space (on the AXI port) with a user-selectable, average read and write delay function.
SystemC mode
- Integrates into your larger SoC system simulation.
- Build more complex SystemC models with real memory subsystem behavior.
- Integrate with other processors to simulate system traffic impacts, DDR controller behaviors, stimulus/activation data generated by other SoC components, and more.
