SystemC TLM Model

The default modeling of data flows in ISS models the memory traffic collectively and stochastically. Transaction Level Model (TLM) is an experimental mode of ISS where each memory transaction is explicitly created and its latency and completion time is individually modeled. This mode better captures bus characteristics such as page boundaries and burst sizes. You can use this when you need to model multiple interdependent data-flows through Chimera. This mode is currently in the alpha stage.

SystemC mode features:

• Integrates into your larger SoC system simulation.
• Build more complex SystemC models with real memory subsystem behavior.
• Integrate with other processors to simulate system traffic impacts, DDR controller behaviors, stimulus/activation data generated by other SoC components, and more.