Cycle Counts for Individual Instructions
To see a more fine-grained breakdown of cycle counts per instruction type, a profile.jsonfile is generated for each ISS run.
An example ISS profile.json file can be found below:
File:
/examples/doc_template/example_profile.jsonLines 1–770[
{
"data": {
"ExecCycles": {
"BRANCH": 130,
"COMPARE": 288,
"COMPUTE": 6692,
"CONDITIONAL": 64,
"CONSTANT_MATERIALIZATION": 1638,
"DATA_MOVEMENT": 32,
"FLOW_SETUP": 436,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 32,
"MAC": 768,
"PREDICATION": 96,
"REG_MOVEMENT": 2741
},
"ExtBytes": {
"LOAD": 219264,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 1809,
"BAR_STORE": 7521,
"BRANCH": 101,
"DEREF_REGPTR_CONFLICT": 0,
"DIV": 0,
"EXT_LOAD": 6095,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 2,
"MEU": 11520,
"MODE_WRITE": 32,
"MUL": 816,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 41168
},
"name": "region: 1 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 113,
"COMPARE": 0,
"COMPUTE": 17783,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 3960,
"DATA_MOVEMENT": 48,
"FLOW_SETUP": 508,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 32,
"MAC": 1536,
"PREDICATION": 0,
"REG_MOVEMENT": 6356
},
"ExtBytes": {
"LOAD": 3584,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 14306,
"BAR_STORE": 7521,
"BRANCH": 56,
"DEREF_REGPTR_CONFLICT": 768,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 0,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 13056,
"MODE_WRITE": 0,
"MUL": 3072,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 69115
},
"name": "region: 2 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 113,
"COMPARE": 0,
"COMPUTE": 17785,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 3960,
"DATA_MOVEMENT": 48,
"FLOW_SETUP": 527,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 32,
"MAC": 1536,
"PREDICATION": 0,
"REG_MOVEMENT": 6356
},
"ExtBytes": {
"LOAD": 5760,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 14306,
"BAR_STORE": 7521,
"BRANCH": 56,
"DEREF_REGPTR_CONFLICT": 768,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 13056,
"MODE_WRITE": 0,
"MUL": 3072,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 69491
},
"name": "region: 3 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 144,
"COMPARE": 1,
"COMPUTE": 27093,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 3983,
"DATA_MOVEMENT": 64,
"FLOW_SETUP": 603,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 48,
"MAC": 1536,
"PREDICATION": 0,
"REG_MOVEMENT": 6445
},
"ExtBytes": {
"LOAD": 8704,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 14306,
"BAR_STORE": 29986,
"BRANCH": 75,
"DEREF_REGPTR_CONFLICT": 772,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 0,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 13056,
"MODE_WRITE": 0,
"MUL": 6144,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 16,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 104272
},
"name": "region: 4 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 116,
"COMPARE": 3,
"COMPUTE": 2704,
"CONDITIONAL": 1,
"CONSTANT_MATERIALIZATION": 547,
"DATA_MOVEMENT": 8,
"FLOW_SETUP": 133,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 4,
"MAC": 256,
"PREDICATION": 0,
"REG_MOVEMENT": 1007
},
"ExtBytes": {
"LOAD": 8704,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 7109,
"BAR_STORE": 2505,
"BRANCH": 31,
"DEREF_REGPTR_CONFLICT": 0,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 2048,
"MODE_WRITE": 0,
"MUL": 256,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 188,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 17271
},
"name": "region: 5 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 27,
"COMPARE": 2,
"COMPUTE": 7748,
"CONDITIONAL": 1,
"CONSTANT_MATERIALIZATION": 1529,
"DATA_MOVEMENT": 300,
"FLOW_SETUP": 174,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 8,
"MAC": 352,
"PREDICATION": 0,
"REG_MOVEMENT": 2083
},
"ExtBytes": {
"LOAD": 4096,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 9502,
"BAR_STORE": 2505,
"BRANCH": 26,
"DEREF_REGPTR_CONFLICT": 675,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 0,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 3104,
"MODE_WRITE": 0,
"MUL": 1216,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 4,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 29256
},
"name": "region: 6 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 27,
"COMPARE": 3,
"COMPUTE": 5927,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 1330,
"DATA_MOVEMENT": 12,
"FLOW_SETUP": 191,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 8,
"MAC": 512,
"PREDICATION": 0,
"REG_MOVEMENT": 2616
},
"ExtBytes": {
"LOAD": 11520,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 4762,
"BAR_STORE": 2505,
"BRANCH": 26,
"DEREF_REGPTR_CONFLICT": 256,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 4864,
"MODE_WRITE": 256,
"MUL": 1024,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 24674
},
"name": "region: 7 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 27,
"COMPARE": 3,
"COMPUTE": 5928,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 1330,
"DATA_MOVEMENT": 12,
"FLOW_SETUP": 191,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 8,
"MAC": 512,
"PREDICATION": 0,
"REG_MOVEMENT": 2616
},
"ExtBytes": {
"LOAD": 9728,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 4762,
"BAR_STORE": 2505,
"BRANCH": 26,
"DEREF_REGPTR_CONFLICT": 256,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 0,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 4864,
"MODE_WRITE": 256,
"MUL": 1024,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 24320
},
"name": "region: 8 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 34,
"COMPARE": 0,
"COMPUTE": 9010,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 1339,
"DATA_MOVEMENT": 16,
"FLOW_SETUP": 219,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 12,
"MAC": 512,
"PREDICATION": 0,
"REG_MOVEMENT": 2127
},
"ExtBytes": {
"LOAD": 16128,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 4762,
"BAR_STORE": 9990,
"BRANCH": 33,
"DEREF_REGPTR_CONFLICT": 257,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 4864,
"MODE_WRITE": 0,
"MUL": 2048,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 35578
},
"name": "region: 9 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 33,
"COMPARE": 3,
"COMPUTE": 981,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 206,
"DATA_MOVEMENT": 1,
"FLOW_SETUP": 83,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 1,
"MAC": 96,
"PREDICATION": 0,
"REG_MOVEMENT": 358
},
"ExtBytes": {
"LOAD": 16128,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 2373,
"BAR_STORE": 0,
"BRANCH": 7,
"DEREF_REGPTR_CONFLICT": 0,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 0,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 960,
"MODE_WRITE": 0,
"MUL": 96,
"NBR_RAW": 0,
"PREDICATION": 0,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 63,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 5261
},
"name": "region: 10 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 649,
"COMPARE": 53,
"COMPUTE": 17879,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 4312,
"DATA_MOVEMENT": 338,
"FLOW_SETUP": 569,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 15,
"MAC": 1280,
"PREDICATION": 1200,
"REG_MOVEMENT": 6774
},
"ExtBytes": {
"LOAD": 146560,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 2371,
"BAR_STORE": 3627,
"BRANCH": 111,
"DEREF_REGPTR_CONFLICT": 848,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 710,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 14560,
"MODE_WRITE": 0,
"MUL": 3136,
"NBR_RAW": 192,
"PREDICATION": 264,
"QLS_Q_FULL": 0,
"RAU": 408,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 59296
},
"name": "region: 11 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 65,
"COMPARE": 1,
"COMPUTE": 587,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 183,
"DATA_MOVEMENT": 24,
"FLOW_SETUP": 77,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 14,
"MAC": 32,
"PREDICATION": 3,
"REG_MOVEMENT": 259
},
"ExtBytes": {
"LOAD": 0,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 912,
"BAR_STORE": 840,
"BRANCH": 35,
"DEREF_REGPTR_CONFLICT": 65,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 448,
"MODE_WRITE": 0,
"MUL": 32,
"NBR_RAW": 0,
"PREDICATION": 14,
"QLS_Q_FULL": 0,
"RAU": 792,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 4738
},
"name": "region: 12 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 746,
"COMPARE": 1904,
"COMPUTE": 12626,
"CONDITIONAL": 1344,
"CONSTANT_MATERIALIZATION": 2111,
"DATA_MOVEMENT": 5060,
"FLOW_SETUP": 487,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 198,
"MAC": 528,
"PREDICATION": 1648,
"REG_MOVEMENT": 6354
},
"ExtBytes": {
"LOAD": 371200,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 3555,
"BAR_STORE": 1252,
"BRANCH": 669,
"DEREF_REGPTR_CONFLICT": 672,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 1775,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 7024,
"MODE_WRITE": 0,
"MUL": 1344,
"NBR_RAW": 88,
"PREDICATION": 1364,
"QLS_Q_FULL": 0,
"RAU": 0,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 50749
},
"name": "region: 13 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 119,
"COMPARE": 1,
"COMPUTE": 886,
"CONDITIONAL": 0,
"CONSTANT_MATERIALIZATION": 305,
"DATA_MOVEMENT": 64,
"FLOW_SETUP": 144,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 18,
"MAC": 16,
"PREDICATION": 3,
"REG_MOVEMENT": 410
},
"ExtBytes": {
"LOAD": 16384,
"STORE": 0
},
"StallCycles": {
"BAR_LOAD": 1216,
"BAR_STORE": 2304,
"BRANCH": 48,
"DEREF_REGPTR_CONFLICT": 101,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 355,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 288,
"MODE_WRITE": 0,
"MUL": 16,
"NBR_RAW": 0,
"PREDICATION": 14,
"QLS_Q_FULL": 0,
"RAU": 2073,
"SPRF_RAW": 0,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 8381
},
"name": "region: 14 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 1330,
"COMPARE": 2643,
"COMPUTE": 14005,
"CONDITIONAL": 1152,
"CONSTANT_MATERIALIZATION": 2934,
"DATA_MOVEMENT": 6742,
"FLOW_SETUP": 1086,
"INTERRUPT": 0,
"ITERATIVE": 0,
"KERNEL_SETUP": 0,
"LOOP_SETUP": 377,
"MAC": 358,
"PREDICATION": 3240,
"REG_MOVEMENT": 8871
},
"ExtBytes": {
"LOAD": 343936,
"STORE": 114688
},
"StallCycles": {
"BAR_LOAD": 4738,
"BAR_STORE": 9694,
"BRANCH": 1481,
"DEREF_REGPTR_CONFLICT": 805,
"DIV": 0,
"EXT_LOAD": 0,
"EXT_STORE": 0,
"INSTRUCTION_FETCH": 2130,
"INTERRUPT": 0,
"LOAD": 0,
"MEU": 7916,
"MODE_WRITE": 0,
"MUL": 1092,
"NBR_RAW": 60,
"PREDICATION": 5520,
"QLS_Q_FULL": 0,
"RAU": 11752,
"SPRF_RAW": 20,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 87946
},
"name": "region: 15 / 15"
},
{
"data": {
"ExecCycles": {
"BRANCH": 3673,
"COMPARE": 4915,
"COMPUTE": 147962,
"CONDITIONAL": 2562,
"CONSTANT_MATERIALIZATION": 29956,
"DATA_MOVEMENT": 12769,
"FLOW_SETUP": 5428,
"INTERRUPT": 1,
"ITERATIVE": 0,
"KERNEL_SETUP": 13,
"LOOP_SETUP": 807,
"MAC": 9830,
"PREDICATION": 6190,
"REG_MOVEMENT": 55560
},
"ExtBytes": {
"LOAD": 1181696,
"STORE": 229376
},
"StallCycles": {
"BAR_LOAD": 90789,
"BAR_STORE": 90276,
"BRANCH": 2781,
"DEREF_REGPTR_CONFLICT": 6312,
"DIV": 0,
"EXT_LOAD": 6095,
"EXT_STORE": 3669,
"INSTRUCTION_FETCH": 7810,
"INTERRUPT": 0,
"LOAD": 2,
"MEU": 101628,
"MODE_WRITE": 544,
"MUL": 24388,
"NBR_RAW": 340,
"PREDICATION": 7176,
"QLS_Q_FULL": 0,
"RAU": 15025,
"SPRF_RAW": 293,
"STORE": 0,
"TENSOR_TABLE_FULL": 0
},
"TotalCycles": 636794
},
"name": "default"
}
]
Instruction Categorization used for Reporting
When reporting profiler results, the Chimera GPNPU instructions executed by ISS are grouped into categories so that users may more easily determine what types of operations are contributing the most to their program's total number of cycles.
The categorization map used to group instructions can be seen below:
File:
/sdk_cli/lib/constants.pyLines 16–56## Cycle Count to Category Mapping for Graphing
COUNT_TO_CATEGORY = {
"ExecCycles": {
"BRANCH": "compute",
"COMPARE": "compute",
"COMPUTE": "compute",
"CONDITIONAL": "compute",
"DATA_MOVEMENT": "data_array",
"ITERATIVE": "compute",
"MAC": "mac",
"PREDICATION": "compute",
"REG_MOVEMENT": "data_array",
"LOOP_SETUP": "compute",
"FLOW_SETUP": "compute",
"CONSTANT_MATERIALIZATION": "compute",
"INTERRUPT": "compute",
"KERNEL_SETUP": "compute",
},
"StallCycles": {
"BRANCH": "compute",
"DEREF_REGPTR_CONFLICT": "compute",
"DIV": "compute",
"EXT_LOAD": "data_external",
"EXT_STORE": "data_external",
"LOAD": "data_ocm",
"MODE_WRITE": "compute",
"PREDICATION": "compute",
"MUL": "compute",
"RAU": "data_ocm",
"SPRF_RAW": "compute",
"STORE": "data_ocm",
"NBR_RAW": "data_array",
"BAR_LOAD": "data_ocm",
"BAR_STORE": "data_ocm",
"INTERRUPT": "compute",
"MEU": "mac",
"QLS_Q_FULL": "data_array",
"TENSOR_TABLE_FULL": "data_ocm",
"INSTRUCTION_FETCH": "compute",
},
}
These instructions categories are further abstractions from the individual RTL instructions being executed by ISS. The map of RTL instructions to execution instruction categories can be referenced below:
NOTE: Stall instruction categories are not included in the map below.
File:
/arch/c++/archsim/src/instructions.cppLines 283–635 switch(inst.get().instType) {
case qasm::InstructionType::DISPATCH: {
qRTL::DispatchInstCode dispatchOpcode = static_cast<qRTL::DispatchInstCode>(inst.get().opCode);
// Default cycle counts, overridden for specific instructions
idec.execCycles = DEFAULT_EXEC_CYCLES;
idec.execCategory = ExecCategory::COMPUTE;
switch(dispatchOpcode) {
case qRTL::DispatchInstCode::NOP:
srcNull();
break;
case qRTL::DispatchInstCode::ORB:
case qRTL::DispatchInstCode::ANDB:
case qRTL::DispatchInstCode::XORB:
case qRTL::DispatchInstCode::XNORB:
case qRTL::DispatchInstCode::SHLB:
case qRTL::DispatchInstCode::SHRLB:
case qRTL::DispatchInstCode::SHRAB:
case qRTL::DispatchInstCode::ADDI32:
case qRTL::DispatchInstCode::SUBI32:
case qRTL::DispatchInstCode::DIVI32:
case qRTL::DispatchInstCode::MAXI32:
case qRTL::DispatchInstCode::MAX32:
case qRTL::DispatchInstCode::MINI32:
case qRTL::DispatchInstCode::MIN32:
case qRTL::DispatchInstCode::MULI32:
case qRTL::DispatchInstCode::MUL32:
case qRTL::DispatchInstCode::MULI16V2:
case qRTL::DispatchInstCode::MUL16V2:
case qRTL::DispatchInstCode::MULI8V4:
case qRTL::DispatchInstCode::MUL8V4:
case qRTL::DispatchInstCode::MULI32LOHI:
case qRTL::DispatchInstCode::MUL32LOHI:
case qRTL::DispatchInstCode::MULI32HI:
case qRTL::DispatchInstCode::MUL32HI:
idec.execCategory = ExecCategory::COMPUTE;
ASSERT(!op1Info.isDeref(), "op1 can not be a memory reference");
src01dst2();
if(dispatchOpcode == qRTL::DispatchInstCode::DIVI32) idec.isDiv = true;
break;
case qRTL::DispatchInstCode::NOTB:
case qRTL::DispatchInstCode::ABSI32:
idec.execCategory = ExecCategory::COMPUTE;
src0dst1();
break;
case qRTL::DispatchInstCode::CSEL:
idec.execCategory = ExecCategory::CONDITIONAL;
src01dst2();
break;
case qRTL::DispatchInstCode::CMPEQ32:
case qRTL::DispatchInstCode::CMPNEQ32:
case qRTL::DispatchInstCode::CMPLT32:
case qRTL::DispatchInstCode::CMPLTE32:
case qRTL::DispatchInstCode::CMPLTI32:
case qRTL::DispatchInstCode::CMPLTEI32:
idec.execCategory = ExecCategory::COMPARE;
src01dst2();
break;
case qRTL::DispatchInstCode::SFS:
case qRTL::DispatchInstCode::SFE:
case qRTL::DispatchInstCode::CRDCR:
case qRTL::DispatchInstCode::CRDCV:
case qRTL::DispatchInstCode::EXPINT:
case qRTL::DispatchInstCode::EXPFRC:
case qRTL::DispatchInstCode::EXPNSCL:
case qRTL::DispatchInstCode::LOGINT:
case qRTL::DispatchInstCode::LOGFRC:
case qRTL::DispatchInstCode::LOGXERR:
case qRTL::DispatchInstCode::LOGYCOR:
idec.execCategory = ExecCategory::ITERATIVE;
break;
case qRTL::DispatchInstCode::JMP:
case qRTL::DispatchInstCode::JAL:
case qRTL::DispatchInstCode::JMPOFF:
src0();
idec.execCategory = ExecCategory::BRANCH;
case qRTL::DispatchInstCode::RET:
idec.execCategory = ExecCategory::BRANCH;
break;
case qRTL::DispatchInstCode::JMPEQ:
case qRTL::DispatchInstCode::JMPNEQ:
case qRTL::DispatchInstCode::JMPEQOFF:
case qRTL::DispatchInstCode::JMPNEQOFF:
case qRTL::DispatchInstCode::JMPLT:
case qRTL::DispatchInstCode::JMPLTE:
case qRTL::DispatchInstCode::JMPLTI:
case qRTL::DispatchInstCode::JMPLTEI:
src01(); // dst is a jump loc
idec.execCategory = ExecCategory::BRANCH;
break;
case qRTL::DispatchInstCode::JMPDECNZ:
case qRTL::DispatchInstCode::JMPINCNE:
src01dst0();
idec.execCategory = ExecCategory::BRANCH;
break;
case qRTL::DispatchInstCode::JMPINCSETUP:
case qRTL::DispatchInstCode::JMPDECSETUP:
src01();
idec.execCategory = ExecCategory::LOOP_SETUP;
break;
case qRTL::DispatchInstCode::CPC:
// op0 is imd and op1 is a core operand
src0dst1();
idec.execCategory = ExecCategory::REG_MOVEMENT;
break;
case qRTL::DispatchInstCode::CP:
src01(); // op2 provides the nbr set
idec.dstFlowSetupReg = isFlowSetupReg(op1Info);
idec.execCategory =
idec.dstFlowSetupReg || isFlowSetupReg(op0Info) ? ExecCategory::FLOW_SETUP : ExecCategory::REG_MOVEMENT;
break;
case qRTL::DispatchInstCode::STCR:
src0dst1(); // op0 will be a constant, op2 provides the nbr set
idec.dstFlowSetupReg = isFlowSetupReg(op1Info);
idec.execCategory = idec.dstFlowSetupReg ? ExecCategory::FLOW_SETUP : ExecCategory::CONST_MAT;
break;
case qRTL::DispatchInstCode::INCLOOPDEPTH:
case qRTL::DispatchInstCode::DECLOOPDEPTH:
idec.execCategory = ExecCategory::LOOP_SETUP;
break;
case qRTL::DispatchInstCode::QL:
idec.execCategory = ExecCategory::DATA_MOVEMENT;
break;
case qRTL::DispatchInstCode::QS:
idec.execCategory = ExecCategory::DATA_MOVEMENT;
break;
case qRTL::DispatchInstCode::QLS:
idec.execCategory = ExecCategory::DATA_MOVEMENT;
break;
case qRTL::DispatchInstCode::BAR:
idec.execCategory = ExecCategory::FLOW_SETUP;
break;
case qRTL::DispatchInstCode::INTR:
src0();
idec.execCategory = ExecCategory::INTERRUPT;
idec.isIntr = true;
break;
default:
FATAL_ERROR("Instruction: " << inst.get().instName << "IMD Opcode: " << inst.get().opCode
<< " not supported!");
break;
}
break;
}
case qasm::InstructionType::CORE_EX: {
qRTL::CoreInstCode coreOpcode = static_cast<qRTL::CoreInstCode>(inst.get().opCode);
idec.execCycles = DEFAULT_EXEC_CYCLES;
idec.execCategory = ExecCategory::COMPUTE;
switch(coreOpcode) {
case qRTL::CoreInstCode::NOP:
srcNull();
break;
case qRTL::CoreInstCode::ORB:
case qRTL::CoreInstCode::ANDB:
case qRTL::CoreInstCode::XORB:
case qRTL::CoreInstCode::XNORB:
case qRTL::CoreInstCode::SHLB:
case qRTL::CoreInstCode::SHRLB:
case qRTL::CoreInstCode::SHRAB:
case qRTL::CoreInstCode::ADDI32:
case qRTL::CoreInstCode::ADDI8V4:
case qRTL::CoreInstCode::ADDI16V2:
case qRTL::CoreInstCode::SUBI32:
case qRTL::CoreInstCode::SUBI8V4:
case qRTL::CoreInstCode::SUBI16V2:
case qRTL::CoreInstCode::DIVI32:
case qRTL::CoreInstCode::MUL32:
case qRTL::CoreInstCode::MULI32:
case qRTL::CoreInstCode::MUL32HI:
case qRTL::CoreInstCode::MULI32HI:
case qRTL::CoreInstCode::MUL32LOHI:
case qRTL::CoreInstCode::MULI32LOHI:
case qRTL::CoreInstCode::MUL8V4:
case qRTL::CoreInstCode::MULI8V4:
case qRTL::CoreInstCode::MUL16V2:
case qRTL::CoreInstCode::MULI16V2:
case qRTL::CoreInstCode::MAXI32:
case qRTL::CoreInstCode::MAXI8V4:
case qRTL::CoreInstCode::MAXI16V2:
case qRTL::CoreInstCode::MAX32:
case qRTL::CoreInstCode::MAX8V4:
case qRTL::CoreInstCode::MAX16V2:
case qRTL::CoreInstCode::MINI32:
case qRTL::CoreInstCode::MINI8V4:
case qRTL::CoreInstCode::MINI16V2:
case qRTL::CoreInstCode::MIN32:
case qRTL::CoreInstCode::MIN8V4:
case qRTL::CoreInstCode::MIN16V2:
idec.execCategory = ExecCategory::COMPUTE;
src01dst2();
if(coreOpcode == qRTL::CoreInstCode::DIVI32) idec.isDiv = true;
break;
case qRTL::CoreInstCode::NOTB:
case qRTL::CoreInstCode::ABSI32:
case qRTL::CoreInstCode::ABSI8V4:
case qRTL::CoreInstCode::ABSI16V2:
case qRTL::CoreInstCode::CLIP:
case qRTL::CoreInstCode::ROUND32:
case qRTL::CoreInstCode::ROUNDE:
idec.execCategory = ExecCategory::COMPUTE;
src0dst1();
break;
case qRTL::CoreInstCode::CSEL:
src01dst2();
idec.execCategory = ExecCategory::CONDITIONAL;
break;
case qRTL::CoreInstCode::CMPEQ32:
case qRTL::CoreInstCode::CMPEQ8V4:
case qRTL::CoreInstCode::CMPEQ16V2:
case qRTL::CoreInstCode::CMPNEQ32:
case qRTL::CoreInstCode::CMPNEQ8V4:
case qRTL::CoreInstCode::CMPNEQ16V2:
case qRTL::CoreInstCode::CMPLTI32:
case qRTL::CoreInstCode::CMPLTI8V4:
case qRTL::CoreInstCode::CMPLTI16V2:
case qRTL::CoreInstCode::CMPLTEI32:
case qRTL::CoreInstCode::CMPLTEI8V4:
case qRTL::CoreInstCode::CMPLTEI16V2:
case qRTL::CoreInstCode::CMPLT32:
case qRTL::CoreInstCode::CMPLT8V4:
case qRTL::CoreInstCode::CMPLT16V2:
case qRTL::CoreInstCode::CMPLTE32:
case qRTL::CoreInstCode::CMPLTE8V4:
case qRTL::CoreInstCode::CMPLTE16V2:
src01dst2();
idec.execCategory = ExecCategory::COMPARE;
break;
case qRTL::CoreInstCode::SFS:
case qRTL::CoreInstCode::SFE:
case qRTL::CoreInstCode::CRDCR:
case qRTL::CoreInstCode::CRDCV:
case qRTL::CoreInstCode::EXPINT:
case qRTL::CoreInstCode::EXPFRC:
case qRTL::CoreInstCode::EXPNSCL:
case qRTL::CoreInstCode::LOGINT:
case qRTL::CoreInstCode::LOGFRC:
case qRTL::CoreInstCode::LOGXERR:
case qRTL::CoreInstCode::LOGYCOR:
srcNull();
idec.execCategory = ExecCategory::ITERATIVE;
break;
case qRTL::CoreInstCode::ACCSUMSH8:
// op0 is the right shift amount
idec.execCategory = ExecCategory::MAC;
src0();
break;
case qRTL::CoreInstCode::PREDPOP:
case qRTL::CoreInstCode::PREDELSE:
case qRTL::CoreInstCode::PREDPUSH:
srcNull();
idec.execCategory = ExecCategory::PREDICATION;
break;
case qRTL::CoreInstCode::ENABLEB:
case qRTL::CoreInstCode::ENABLEC:
case qRTL::CoreInstCode::DISABLEB:
case qRTL::CoreInstCode::DISABLEC:
srcNull();
idec.execCategory = ExecCategory::PREDICATION;
break;
case qRTL::CoreInstCode::CP:
src0dst1();
idec.execCategory = ExecCategory::REG_MOVEMENT;
break;
case qRTL::CoreInstCode::STCR:
src0dst1();
idec.execCategory = ExecCategory::CONST_MAT;
break;
default:
FATAL_ERROR("Instruction: " << inst.get().instName << "Core Opcode: " << inst.get().opCode
<< " not supported!");
break;
}
} break;
case qasm::InstructionType::CORE_NB: {
qRTL::NbInstCode nbOpcode = static_cast<qRTL::NbInstCode>(inst.get().opCode);
idec.execCycles = DEFAULT_EXEC_CYCLES;
idec.execCategory = ExecCategory::DATA_MOVEMENT;
switch(nbOpcode) {
case qRTL::NbInstCode::NNOP:
srcNull();
break;
case qRTL::NbInstCode::NRB:
src0dst1();
idec.oppOfPortWritten = opposite(op1Info.nbSet);
idec.oppOfPortValidWritten = idec.oppOfPortWritten;
break;
case qRTL::NbInstCode::NNB:
srcNull();
idec.nbrPortRead = (1 << op0Info.nbrCore);
idec.oppOfPortWritten = opposite(op1Info.nbSet);
idec.nbrPortValidRead = idec.nbrPortRead;
idec.oppOfPortValidWritten = idec.oppOfPortWritten;
break;
case qRTL::NbInstCode::NNBR:
srcNull();
// All nbr ports are read and written
idec.nbrPortRead = (1 << qRTL::Neighbor::NORTH) | (1 << qRTL::Neighbor::SOUTH) |
(1 << qRTL::Neighbor::EAST) | (1 << qRTL::Neighbor::WEST);
idec.oppOfPortWritten = opposite(idec.nbrPortRead);
idec.nbrPortValidRead = idec.nbrPortRead;
idec.oppOfPortValidWritten = idec.oppOfPortWritten;
break;
case qRTL::NbInstCode::NSV:
case qRTL::NbInstCode::NCV:
srcNull();
idec.nbrPortValidRead = 0;
idec.oppOfPortValidWritten = opposite(op0Info.nbSet);
break;
}
} break;
Execution Cycles vs. Stall Cycles
The categorization map in the previous section distinguishes between execution cycles, i.e. ExecCycles, and stall cycles, i.e. StallCycles:
- Execution cycles are performant instructions being executed by the GPNPU.
- Stall cycles are cycles where the pipeline is stalled waiting for dependent execute cycles to complete.
Instruction Category Definitions
| Instruction Category | Definition | Example |
|---|---|---|
BRANCH (Execute) | Instructions that can cause the GPNPU to begin executing a different instruction sequence and thus deviate from its default behavior of executing instructions in order. | A single line if conditional statement or a return statment. |
COMPARE | Instructions that compare register values. | Boolean expressions such as a >= 100. |
COMPUTE | General ALU instructions. | Basic arithmetic expressions such as addition, e.g. a + 20, or boolean operators, e.g. a & b. |
CONDITIONAL | Conditional variable assignment instructions. | In C, a conditional assignment operation such as result = condition ? A : B; . |
DATA_MOVEMENT | Movement of data across neighboring PEs. Note: Data movement is restricted to bordering PEs in the North/South/East/West directions. | |
ITERATIVE | iterative numerical algorithms with hw support, e.g. cordic, log, exp | |
MAC | Setup cycles for MEU (MAC execution unit). Note: The total time taken by the MEU to finish executing the MAC operations are accounted for by the MEU instruction category lower in this table. | |
PREDICATION | if/else statements used to select between multi-line code blocks. Note: the code inside of the code blocks does not count towards PREDICATION cycle count. | |
REG_MOVEMENT | Register movements/copies within a PE. | |
LOOP_SETUP | Setup for for loops. | |
FLOW_SETUP | Setup for flows. | |
CONSTANT_MATERIALIZATION | Cycles spent copying a constant to a register. | Register write assembly instruction, such as a dispatcher copy:dcp 0x23243 r10 |
INTERRUPT (Execute) | An interrupt instruction that causes the GPNPU to interrupt the host. May or may not halt GPNPU execution. | |
KERNEL_SETUP | Setup kernels. | |
BRANCH (Stall) | Stall cycle due to a BRANCH execution instruction. | |
DEREF_REGPTR_CONFLICT | Stall cycles between updating a register pointer and the use of the register pointer. | |
DIV | The stall cycles while executing a div instruction. | |
EXT_LOAD | Stall cycle due to data being loaded from external memory (external DMA transfer) that is needed to continue program execution. | |
EXT_STORE | Stall cycle due to data being stored to external memory (external DMA transfer) that is needed to continue program execution. | |
LOAD | Stall cycle due to data being loaded from internal memory (internal DMA transfer) that is needed to continue program execution. | |
MODE_WRITE | Stall cycles due to switching data modes, i.e. 8b, 16b, 32b, of read after write (RAW) instructions. | |
PREDICATION | Stall cycles waiting for a PREDICATION condition, e.g. if/then/else, to resolve.Note: Some speculation to the direction a PREDICATION condition is done, but those cycles are counted as execution cycles and not stalls. | |
MUL | The stall cycles if any between a mul instruction and the usage of the output from it. | |
RAU | Stall cycle waiting for a RAU (random access unit) to complete memory movement. | |
SPRF_RAW | Stall cycles to do a back-to-back read and write from the register file. Note: SPRF_RAW is an acronym for "Single Ported Register File - Read After Write". | |
STORE | Stall cycle due to data being stored to internal memory (internal DMA transfer) that is needed to continue program execution. | |
NBR_RAW | Stall cycles when a neighbor port, e.g. North/South/East/West, is written to and then used in the very next cycles. Note: NBR_RAW is an acronym for "Neighbor Broadcast Register - Read After Write". | |
BAR_LOAD | Stall cycle due to data being loaded from internal memory (memory transfer using flow mesh) that is needed to continue program execution. | |
BAR_STORE | Stall cycle due to data being stored to internal memory (memory transfer using flow mesh) that is needed to continue program execution. | |
INTERRUPT (Stall) | Stall cycles due to an interrupt. | |
MEU | Stall cycles waiting for MAC execution to complete. | |
QLS_Q_FULL | Stall cycles waiting for the PE array <--> L2 queue to drain. | |
TENSOR_TABLE_FULL | Stall cycles spent waiting for the tensor table to clear. Note: Currently, only 4 tensors can be alive at a time. If a 5th tensor is attempted to be allocated, the stall cycles will begin. | |
INSTRUCTION_FETCH | Stall cycle waiting for fetching of an instruction. |
RTL Instruction Definitions
| RTL Instruction | Definition |
|---|---|
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::NOPqRTL::DispatchInstCode::NOP | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::ORBqRTL::DispatchInstCode::ORB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::ANDBqRTL::DispatchInstCode::ANDB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::XORBqRTL::DispatchInstCode::XORB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::XNORBqRTL::DispatchInstCode::XNORB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::SHLBqRTL::DispatchInstCode::SHLB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::SHRLBqRTL::DispatchInstCode::SHRLB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::SHRABqRTL::DispatchInstCode::SHRAB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::ADDI32qRTL::DispatchInstCode::ADDI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::SUBI32qRTL::DispatchInstCode::SUBI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::DIVI32qRTL::DispatchInstCode::DIVI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MAXI32qRTL::DispatchInstCode::MAXI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MAX32qRTL::DispatchInstCode::MAX32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MINI32qRTL::DispatchInstCode::MINI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MIN32qRTL::DispatchInstCode::MIN32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MULI32qRTL::DispatchInstCode::MULI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MUL32qRTL::DispatchInstCode::MUL32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MULI16V2qRTL::DispatchInstCode::MULI16V2 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MUL16V2qRTL::DispatchInstCode::MUL16V2 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MULI8V4qRTL::DispatchInstCode::MULI8V4 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MUL8V4qRTL::DispatchInstCode::MUL8V4 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MULI32LOHIqRTL::DispatchInstCode::MULI32LOHI | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MUL32LOHIqRTL::DispatchInstCode::MUL32LOHI | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MULI32HIqRTL::DispatchInstCode::MULI32HI | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::MUL32HIqRTL::DispatchInstCode::MUL32HI | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::NOTBqRTL::DispatchInstCode::NOTB | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::ABSI32qRTL::DispatchInstCode::ABSI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CSELqRTL::DispatchInstCode::CSEL | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CMPEQ32qRTL::DispatchInstCode::CMPEQ32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CMPNEQ32qRTL::DispatchInstCode::CMPNEQ32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CMPLT32qRTL::DispatchInstCode::CMPLT32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CMPLTE32qRTL::DispatchInstCode::CMPLTE32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CMPLTI32qRTL::DispatchInstCode::CMPLTI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CMPLTEI32qRTL::DispatchInstCode::CMPLTEI32 | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::SFSqRTL::DispatchInstCode::SFS | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::SFEqRTL::DispatchInstCode::SFE | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CRDCRqRTL::DispatchInstCode::CRDCR | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CRDCVqRTL::DispatchInstCode::CRDCV | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::EXPINTqRTL::DispatchInstCode::EXPINT | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::EXPFRCqRTL::DispatchInstCode::EXPFRC | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::EXPNSCLqRTL::DispatchInstCode::EXPNSCL | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::LOGINTqRTL::DispatchInstCode::LOGINT | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::LOGFRCqRTL::DispatchInstCode::LOGFRC | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::LOGXERRqRTL::DispatchInstCode::LOGXERR | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::LOGYCORqRTL::DispatchInstCode::LOGYCOR | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPqRTL::DispatchInstCode::JMP | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JALqRTL::DispatchInstCode::JAL | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPOFFqRTL::DispatchInstCode::JMPOFF | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::RETqRTL::DispatchInstCode::RET | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPEQqRTL::DispatchInstCode::JMPEQ | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPNEQqRTL::DispatchInstCode::JMPNEQ | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPEQOFFqRTL::DispatchInstCode::JMPEQOFF | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPNEQOFFqRTL::DispatchInstCode::JMPNEQOFF | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPLTqRTL::DispatchInstCode::JMPLT | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPLTEqRTL::DispatchInstCode::JMPLTE | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPLTIqRTL::DispatchInstCode::JMPLTI | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPLTEIqRTL::DispatchInstCode::JMPLTEI | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPDECNZqRTL::DispatchInstCode::JMPDECNZ | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPINCNEqRTL::DispatchInstCode::JMPINCNE | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPINCSETUPqRTL::DispatchInstCode::JMPINCSETUP | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::JMPDECSETUPqRTL::DispatchInstCode::JMPDECSETUP | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CPCqRTL::DispatchInstCode::CPC | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::CPqRTL::DispatchInstCode::CP | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::STCRqRTL::DispatchInstCode::STCR | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::INCLOOPDEPTHqRTL::DispatchInstCode::INCLOOPDEPTH | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::DECLOOPDEPTHqRTL::DispatchInstCode::DECLOOPDEPTH | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::QLqRTL::DispatchInstCode::QL | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::QSqRTL::DispatchInstCode::QS | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::QLSqRTL::DispatchInstCode::QLS | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::BARqRTL::DispatchInstCode::BAR | |
File: /arch/c++/archsim/src/instructions.cppSymbol: qRTL::DispatchInstCode::INTRqRTL::DispatchInstCode::INTR | |
| TODO: Add CoreInstCodes |
