Chimera™ GPNPU processors
Modern System-on-Chip (SoC) architectures designed for AI deploy complex applications that mix traditional C++ algorithms with newly emerging and fast-changing Deep Neural Network (DNN) inference code.
Today, SoC designers build systems with dedicated compute nodes for each of these types of algorithms. This forces the software developers targeting these systems to artificially partition their applications between two or three different kinds of processors, e.g. a Neural Processing Unit (NPU) and a Digital Signal Processor (DSP).
In comparison, Quadric's GPNPU architecture is designed from the ground-up to have high compute-utilization for inference and run complex, data-parallel C++ algorithms on the same, fully-programmable processor core.
Blending the best attributes of a NPU and a DSP, Chimera GPNPUs can handle the entire application workload found in highly-parallel, data-rich processing pipelines. Further, Quadric's Chimera processor architecture significantly improves developer productivity, performance fidelity, and future-proof flexibility because programmers only need to write code for a single processor core.
Key Benefits
- Software development productivity: Run DSP and ML code on one processor – there’s no need to artificially partition your application.
- Scalable performance: code written for one Chimera core runs at-speed on other QB Series family cores.
- Hardware simplicity: Integrate a single GPNPU core instead of a CPU plus DSP plus NPU.
- Future-proof, no-limits machine learning: A fully C++ programmable processor that can run any Neural Network (NN) graph operator in a high-performance, parallel implementation.
- High multiply-accumulate (MAC) utilization: Delivers highly competitive inferences-per-second throughput in comparison to dedicated Neural Network accelerators while maintaining programmability.
- Ease of Development: Prototype applications using the Quadric DevStudio cloud-based GUI or develop custom kernels on-premise with the Chimera SDK, conveniently bundled in a container.
QB Series Processors - From 1 TOP/s to 16 TOP/s
The Quadric 2nd generation, i.e. QB series, release of Chimera GPNPUs offers three levels of compute performance:
| QB Series Product | Machine Learning Performance | DSP Performance |
|---|---|---|
| Chimera QB1 | 1 TOPS | 64 GOPS |
| Chimera QB4 | 4 TOPS | 256 GOPS |
| Chimera QB16 | 16 TOPS | 1 TOPS |
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|---|
| Chimera Processor Block Diagram |
Key Features of the Chimera GPNPU processors
- Hybrid Von Neuman + 2D SIMD matrix architecture.
- 64b Instruction word, single-instruction issue per clock.
- 7-stage, in-order pipeline.
- Scalar / Vector / Matrix instructions modelessly intermixed with granular predication.
- Deterministic, non-speculative execution delivers predictable performance levels.
- No exceptions (runs bare metal code under supervision of a system host CPU).
- AXI Interfaces to system memory (independent data and instruction access).
- Instruction cache (256K).
- Local Register Memory (LRM) with data broadcast networks within matrix array allows overlapped compute and data movement to maximize performance.
- Large local 2nd-level data memory (multi-bank, configurable 2MB to 32MB) minimizes off-chip DDR access, lowering power dissipation.
- Optimized for INT8 machine learning inference (with optional INT16 support).
- Compiler-driven, fine-grained clock gating delivers power savings.
Rich DSP and Matrix Instruction Set
The Chimera instruction set implements a rich set of operations covering the breadth of control, DSP, and tensor graph processing. The Chimera Processing Elements (PE) are optimized for 8-bit integer (INT8) graph operations with a configurable hardware option to also include 16bit MAC hardware. In addition to the NN-focused hardware, a full set of math functions is available in each ALU – both in the Scalar Element and the Processing Element (PE) units – to support all forms of complex DSP operations, including:
- 32bit Integer MUL / ADD / SUB / Compare.
- 32bit Integer DIV (iterative execution).
- 32bit Cordic function unit (Sine, cosine, Rect. to Polar / Polar to Rect., ArcX functions).
- Logarithmic and Exponential functions.
A set of math function libraries, harnessing these special function instructions, accompanies the Chimera SDK. These common math libraries cover an array of common signal processing routines including cordic, linear algebra, filtering and image processing functions.
Memory Hierarchy
All Chimera architectures contain three levels of memory. They are listed below in order below from most expensive to least expensive to access:
- External Memory (often DDR)
- L2 Memory: shared SRAM across all Processing Elements (PE)
- Local Register Memory (LRM): local SRAM dedicated to each PE
Compute on high-dimensional data is carried out in Chimera processor's PEs. Data can be transferred to and from each PE's LRM using CCL's data access APIs.
The goal of any programmer should be to keep data in the LRM for as long as possible when mapping algorithms.
